The present invention concerns the use of symbolic routing guidance in VLSI circuit design for special connection networks such as power, clock, and ground connection networks.
Once the logic circuitry for a very large scale integrated (VLSI) circuit has been designed, placement algorithms are used to place the VLSI circuit logic efficiently upon a chip. The integrated circuit is generally divided into component blocks of logic circuits. The logic circuits are often referred to as logic cells. Each of the component blocks occupies a fixed area when placed on the chip. Each component block is connected to other component blocks through wire networks, also called connection networks. These connection networks have a measurable width and take up space on the integrated circuit which is directly proportional to their length.
On the chip, locations are selected in which to place the component blocks so that the area on the integrated circuit is optimally utilized. Optimal placement of component blocks occurs when the dead space, that is area between component blocks which is not utilized by component blocks, is minimized, and when the total area of connection networks within component blocks and between component blocks will be minimized.
Once component blocks are placed on an integrated circuit, the routing of connection networks within the component blocks and between component blocks is performed. These connection networks are used to interconnect logic circuitry within the integrated circuit.
In addition to the routing of connection networks used to interconnect logic circuitry within the integrated circuit, it is also necessary to route special wire networks, for example, connection networks of ground wires, power wires and clock wires. In the prior art, automatic routers used for placement of these special wire networks have produced physical layout of wire networks as they are to be placed on the chip. For descriptions of prior art methods for routing special wire networks, see for example, Andrew S. Moulton, Laying the Power and Ground Wires on a VLSI Chip, 20th Design Automation Conference, IEEE, 1983, pp. 754-755. See also, David W. Russell, Hierarchical Routing of Single Layer Metal Trees in Compiled VLSI, ICCAD, IEEE, 1985, pp. 270-272.